Computer architecture / SystemVerilog · RV32I
RISC-V single-cycle CPU.
A tutorial-based single-cycle processor project that I use to study how instructions turn into control signals and data movement.
View repository ↗One instruction, one datapath
The design brings together a program counter, control unit, register file, ALU, immediate generation, and memory modules. It targets a subset of the RV32I instruction set, with fetch, decode, execution, memory access, and write-back in a single cycle.
Concepts explored
- Instruction decoding and control signals
- Register reads, ALU operations, and write-back
- Branches, immediate values, and program-counter updates
Project notes
This is a learning implementation with documented bugs and missing instructions. Full RV32I compliance, a self-checking testbench, and pipelining are future work.